1. Field of the Invention
The present invention relates to power-on reset circuits and, more particularly, to a wideband power-on reset circuit that has a glitch-free output.
2. Description of the Related Art
When a DC power supply is initially switched on, its output voltage rises and ultimately stabilizes at a specified DC value. The time interval from when the power supply is initially switched on, to when its output voltage finally stabilizes, is often referred to as the “power-on reset interval” or the “cold initialization interval”.
All on-chip circuits that are connected to the power supply must be forced into their correctly initialized states during cold initialization. If the on-chip circuits are not properly initialized, the circuits could generate false output signals during initialization, or enter the wrong initialized state. Both of these possibilities can cause erratic system behavior and/or system failure.
For chips that derive their DC (VDD) supply voltage from an AC line, the cold initialization interval cannot be less than 4 ms (¼ cycle of the 60 cycle AC line). However, in most cases the cold initialization interval can last considerably longer than this, depending on the rise time specifications of the power supply. Alternatively, for chips that are directly powered from a battery, the cold initialization interval can be extremely short, on the order of a few microseconds.
If the system includes a crystal oscillator, the cold initialization interval must be extended to include a crystal warm-up delay. This warm-up delay must provide sufficient time for the crystal to begin oscillating at the desired frequency, with the desired accuracy. For most crystals, the required warm-up delay is relatively long, on the order of 25 ms to 250 ms.
The cold initialization interval is typically generated by a power-on reset (POR) circuit. Ideally, the POR circuit is a completely on-chip circuit that does not require any package pins or external components, such as a resistor and/or a capacitor. However, when the cold initialization interval must be extended to include a crystal warm-up delay, it is not practical to employ an on-chip RC time constant in order to generate the required warm-up delay.
For example, assuming that the maximum practical value of an on-chip capacitor is 100 pF, a 2500 MΩ resistor would be required in order to generate a 250 ms time delay. However, it is not practical to implement a 2500 MΩ resistor on-chip for two reasons: 1) the chip area consumed would be extremely large, and 2) the resistor current would not be reliable because it would be extremely small (i.e. on the order of 1 nA at 3.3V).
In summary, if the cold initialization interval includes a crystal warm-up delay, a POR circuit cannot use on-chip RC components to generate the crystal warm-up delay. This implies that the POR circuit must be “ratiometric” to the VDD voltage. In other words, the output of the POR circuit must only depend upon the value of the VDD voltage, not upon the ramp rate of the VDD voltage.
Furthermore, a “valid” (sufficiently high) VDD voltage is not available during most of the cold initialization interval because the VDD voltage is ramping up during this interval. As a result, a POR circuit must be able to operate correctly, even when a “valid” VDD voltage is not present.
In addition, a POR circuit must not generate an erroneous reset signal in response to noise on the DC (VDD) power supply line. Power supply line noise can be due to many factors, including simultaneously switching I/O circuits (SSO switching), high speed logic gate switching and high power supply ripple.
Due to the limitations described above, there is a need for an on-chip POR circuit that can generate a crystal warm-up delay without requiring any external components or package pins. Furthermore, the POR circuit must not depend upon the VDD voltage ramp rate or the presence of a valid VDD voltage during most of the cold initialization interval. In addition, the POR circuit must not erroneously respond to noise on the DC (VDD) power supply line.